change an interrupt handler in real mode

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Sorry for the edit, but: It's a pentium D processor and the assembler I'm using is nasm. I would like to set up an interrupt table for real mode.

It's something like this:

Last edited by kmalloc on 15 Feb 2014, 4:00 am, edited 1 time in total.

Which architecture are you coding for? I'm no programmer, but I think it would help if you were more specific about what type of CPU you were working on. Since you mentioned "real mode", I'm going to assume x86.

It's a pentium D processor. I will like to have more knowledge of real mode and I'm stuck.

Looks to me like he's posted pure machine code. If he posts the assembler version of the code we might better be able to help. It would also help if he said what processor he's coding for.

Ah yes, hadn't noticed that. So all he's posted is a numerical sequence, it isn't even code. Back in the day (long ago) when I did assembly programming for the 6502 processor messing with interrupts was something done with great care. I had a Commodore 64 and my program code used to take over the entire computer banking out the operating system ROM to use the RAM at the same shared address. My code handled all the interrupts as necessary. That was long ago though... in a galaxy far away. LOL.

You're misunderstanding what the table is supposed to contain; all you've constructed is a list of numbers (constants) where you should have had a list of destination addresses.
Check out the syntax of DW: http://www.nasm.us/xdoc/2.11/html/nasmd ... tion-3.2.1

Each 4-byte offset into the table points to a seg:ofs destination address - the address of the code which handles that particular interrupt.
So the first entry at offset zero is the address of the code to handle interrupt 0, the second entry at offset 4 is the address of the code to handle int 1, the third at offset 8 is the address for int 2 - and so on.

Here's a worked example in NASM of reading and altering the table:
http://computer-programming-forum.com/4 ... 10cbdb.htm
That code uses a DOS environment to allow it to be executed, but the essential parts are not OS-related; one way of writing an entry is basically this: (obviously ES and CS need to have sane values established elsewhere)

Because all x86 processors start in real mode when reset and in order to load an OS (the OP is working on a bootloader), certain operational conditions must be established first.